CMOS-Compatible Microfabrication Technology for High-Quality Piezoelectric Thin Films

Existing process technologies for integration of piezoelectric thin films into microsystems have been limited in various ways, including low piezoelectric coupling, limited maximum film thickness, low repeatability, and high-temperature processing. As an alternative, we introduced a new CMOS-compatible microfabrication technology, which allows wafer-level integration of bulk piezoelectric ceramics on silicon while preserving their original ferroelectric and piezoelectric properties. The developed processes include low-temperature gold-indium diffusion bonding of a bulk PZT or PMN-PT substrate on silicon, an enhanced lapping/polishing process to obtain a final film thickness of 5-100 μm with high precision and wafer-level uniformity (±0.5 μm), and various PZT thin/thick film patterning processes by wet-etching, dry-etching, and femto/nano-second laser ablation. This process is also extended to realize a stack of piezoelectric thin films, and suspended structures via surface micromachining. Currently, the introduced technology can provide the highest electromechanical coupling (kij2) and piezoelectric strain coefficient (dij) among other thin-film deposition methods.

Related Publications:

E. E. Aktakka, R. L. Peterson, K. Najafi, “Wafer-level integration of high-quality bulk piezoelectric ceramics on silicon” IEEE Transactions on Electron Devices, vol. 60, pp. 2022-2030, 2013.

E. E. Aktakka, R. L. Peterson, K. Najafi, “Wet-etching and uniform wafer-level thinning of bulk piezoelectric ceramics on silicon”, Solid- State Sensors, Actuators, and Microsystems Workshop (Hilton Head 2012), Hilton Head Island, USA, pp. 256-257, June 2012.